MCQ Subject: Computer Organisation & Architecture

In a typical multi-level cache hierarchy, which of the following accurately describes the relationship between cache levels and their distance from the CPU?

In a multi-core CPU, which cache coherence protocol uses states such as ‘Modified’, ‘Exclusive’, ‘Shared’, and ‘Invalid’?

In a pipelined processor, which stage is primarily responsible for a stall when the CPU waits for an instruction to be fetched from the main memory due to a cache miss?

What is the primary function of the Memory Management Unit (MMU) in a computer system?

In a multi-core processor system with a shared main memory, which protocol ensures cache coherence by invalidating outdated copies of a data block across all cores when one core modifies it?

Which ILP technique involves executing more than one instruction per clock cycle by using multiple execution units?

In a typical cache memory hierarchy, which level of cache is usually the closest to the CPU?

Which CPU architecture explicitly defines instruction-level parallelism (ILP) during the compilation phase by specifying multiple operations in a single instruction, allowing for predefined parallel execution?

Which ILP technique involves executing multiple instructions in a single clock cycle by dividing the pipeline into stages?

A pipeline stall occurs because the processor waits for a branch instruction to resolve. What hazard type does this describe?