MCQ Subject: Computer Organisation & Architecture

In a pipelined CPU, which technique directly transfers an operand from a later instruction’s execution stage to an earlier instruction’s execution stage to resolve a data hazard?

What is the primary purpose of implementing a cache hierarchy in computer systems?

In the MESI cache coherence protocol, if a processor writes to a cache line currently in the Shared state across multiple caches, what happens to the state of that line in the writing processor’s cache and the other caches?

Which CPU architecture is characterized by fixed-length instructions, emphasizing simplicity for efficient pipelining and faster execution?

In a CPU pipeline, a stall occurs in the execution stage due to a dependency on the result of a previous instruction. If Instruction 1 loads a value into register R1 and Instruction 2 immediately uses R1 for a calculation, what type of dependency causes the stall?

What is the name of the bottleneck occurring in architectures that use a single bus for both instruction and data transfer, as in the Von Neumann Architecture?

In a typical 5-stage CPU pipeline, which stage is MOST LIKELY to handle the calculation of the effective memory address for a load instruction?

In a computer system with a multi-level cache hierarchy, which optimization strategy MOST DIRECTLY improves the overall cache performance?

In a pipelined processor, which of the following is MOST DIRECTLY affected by an increase in latency of a single pipeline stage?

Which architecture type is characterized by using simple instructions that can be combined to perform more complex operations, aiming for efficient pipelining and faster execution?