MCQ Subject: Computer Organisation & Architecture

Which cache replacement policy discards the block that has not been accessed for the longest time since its last use?

In a pipelined processor, the primary function of the Instruction Decode (ID) stage is to:

In a cache memory system with a fixed size, which replacement policy is primarily designed to minimize page faults by replacing the least recently used page?

Which computer architecture is characterized by a focus on simple, highly pipelined instructions to achieve high performance through efficient execution rather than complex instructions?

What is the primary benefit of implementing pipelining in a processor’s architecture?

Which cache coherence protocol employs Modified, Exclusive, Shared, and Invalid states to manage multi-core cache consistency?

Which cache coherence protocol ensures a cache line can be modified by only one processor at a time, using states to track shared and exclusive access efficiently?

In a 5-stage pipeline (Fetch, Decode, Execute, Memory, Writeback), an ‘ADD’ instruction follows a ‘LOAD’ instruction. Assume the ‘ADD’ instruction depends on the data loaded by ‘LOAD’. Why does the pipeline stall occur?